A continuing goal in integrated circuitry fabrication is to make ever smaller and closer packed circuit components. As integrated circuitry density has increased, there is often greater reduction in the horizontal dimension of circuit components as compared to the vertical dimension. In many instances, the vertical dimension has increased. As size decreases and density increases, there is a continuing challenge to provide sufficient conductive contact area between electrically coupled circuit components particularly where that coupling is through contacting surfaces that are substantially horizontal. For example, elevationally elongated conductive vias formed in contact openings are commonly used for electrically coupling circuit components that are at different elevations relative to one another. The contact openings may need to be etched through dielectric material to different elevations within the substrate, and which can be problematic. As circuit components become smaller and closer together, it becomes increasingly difficult to control critical dimension, mask alignment, and provide acceptable margins of error when forming contact openings to lower elevation circuit components.
Different regions of semiconductor devices (e.g., integrated circuits) are commonly laterally separated from one another by vertically-extending dielectric isolation regions formed in bulk or other semiconductor material. Additionally, vertically-extending isolation regions may be formed within an individual region to electrically separate circuit components therein (e.g., within a region comprising a plurality of closely-spaced repeating components). Those isolation regions may be laterally narrower than vertical isolation regions used primarily to electrically separate larger and/or different circuitry regions of the substrate from one another. Nevertheless, all such vertical isolation regions are typically formed at the same time initially by etching followed by subsequent fill with one or more dielectric materials. In some instances, the fill material is initially liquid, partially fills the individual trenches, and is subsequently hardened. Additional solid dielectric material is deposited over the solidified dielectric material. The substrate is then typically subjected to annealing conditions towards achieving a desired finished composition and structure for the dielectric isolation material. Such processing can produce different lateral stresses in semiconductor material of the substrate in part due to typical different lateral widths of these isolation regions. This may lead to dislocations or other adverse attributes in semiconductor material of the substrate.
Memory is one type of integrated circuitry commonly incorporating conductive vias and vertical isolation regions. Integrated memory is usually fabricated in one or more arrays of individual memory cells. The memory cells might be volatile, semi-volatile, or nonvolatile. Nonvolatile memory cells can store data for extended periods of time in the absence of power. Nonvolatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates, and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds, or less. The memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.